IT999210B - Circuito di suddivisione utiliz zante un segnale esterno di interruzione - Google Patents

Circuito di suddivisione utiliz zante un segnale esterno di interruzione

Info

Publication number
IT999210B
IT999210B IT30932/73A IT3093273A IT999210B IT 999210 B IT999210 B IT 999210B IT 30932/73 A IT30932/73 A IT 30932/73A IT 3093273 A IT3093273 A IT 3093273A IT 999210 B IT999210 B IT 999210B
Authority
IT
Italy
Prior art keywords
interrupt signal
external interrupt
subdivision circuit
subdivision
circuit
Prior art date
Application number
IT30932/73A
Other languages
English (en)
Italian (it)
Inventor
F Nickel
J Swanson
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Application granted granted Critical
Publication of IT999210B publication Critical patent/IT999210B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Studio Circuits (AREA)
  • Hardware Redundancy (AREA)
  • Storage Device Security (AREA)
IT30932/73A 1972-11-06 1973-11-05 Circuito di suddivisione utiliz zante un segnale esterno di interruzione IT999210B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00304172A US3832695A (en) 1972-11-06 1972-11-06 Partitioning circuit employing external interrupt signal

Publications (1)

Publication Number Publication Date
IT999210B true IT999210B (it) 1976-02-20

Family

ID=23175390

Family Applications (1)

Application Number Title Priority Date Filing Date
IT30932/73A IT999210B (it) 1972-11-06 1973-11-05 Circuito di suddivisione utiliz zante un segnale esterno di interruzione

Country Status (10)

Country Link
US (1) US3832695A (en])
JP (1) JPS5710463B2 (en])
CA (1) CA1008182A (en])
CH (1) CH600432A5 (en])
DE (1) DE2354522C3 (en])
FR (1) FR2206014A5 (en])
GB (1) GB1451349A (en])
IT (1) IT999210B (en])
NL (1) NL7315159A (en])
SE (1) SE396148B (en])

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5124395U (en]) * 1974-08-12 1976-02-23
DE2742035A1 (de) * 1977-09-19 1979-03-29 Siemens Ag Rechnersystem
US4484270A (en) * 1982-07-07 1984-11-20 Sperry Corporation Centralized hardware control of multisystem access to shared and non-shared subsystems
JPS5922120A (ja) * 1982-07-28 1984-02-04 Fanuc Ltd システム作成方式
EP0237841B1 (de) * 1986-03-21 1991-07-24 Siemens Aktiengesellschaft Verfahren zur Bearbeitung von Konfigurationsänderungen einer Datenverarbeitungsanlage und Vorrichtung zur Durchführung des Verfahrens
JPS63271587A (ja) * 1987-04-28 1988-11-09 Kyoritsu:Kk コ−ドシステム
JPS63273184A (ja) * 1987-04-30 1988-11-10 Kyoritsu:Kk コ−ドシステム
AU3594189A (en) * 1988-06-21 1990-01-04 Amdahl Corporation Controlling the initiation of logical systems in a data processing system with logical processor facility
GB2350212B (en) * 1999-02-09 2003-10-08 Adder Tech Ltd Data routing device and system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1069910B (de) * 1958-03-01 1959-11-26 Standard Elektrik Lorenz Aktiengesellschaft, Stuttgart-Zuffenhausen Kommandowerk mit Indexregister
US3386082A (en) * 1965-06-02 1968-05-28 Ibm Configuration control in multiprocessors
US3544973A (en) * 1968-03-13 1970-12-01 Westinghouse Electric Corp Variable structure computer
US3680052A (en) * 1970-02-20 1972-07-25 Ibm Configuration control of data processing system units

Also Published As

Publication number Publication date
CH600432A5 (en]) 1978-06-15
DE2354522B2 (de) 1978-04-20
FR2206014A5 (en]) 1974-05-31
US3832695A (en) 1974-08-27
CA1008182A (en) 1977-04-05
DE2354522C3 (de) 1978-12-07
DE2354522A1 (de) 1974-05-16
GB1451349A (en) 1976-09-29
AU6204673A (en) 1975-05-01
NL7315159A (en]) 1974-05-08
SE396148B (sv) 1977-09-05
JPS4996654A (en]) 1974-09-12
JPS5710463B2 (en]) 1982-02-26

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